// (C) 2021 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

module dcscm_main
#(parameter SCM_FPGA_REV = 8'h00, SCM_FPGA_REV_TEST = 8'h00)
(
	//Input CLK
	input        	iClk_2M,
   input        	iRST_N,
	
	//SCM_AUX
	input				PWRGD_P1V05_SCM_AUX,
	input				PWRGD_P1V0_BMC_AUX,
	input				RST_DEDI_BUSY_CPU0_N,
	input				RST_DEDI_BUSY_CPU1_N,
    input           iSCM_BMC_EN,
    input           iCPU1_AUX_PWR_OK,                // From main FPGA through LTPI, indicate CPU1 AUX power rails are fully on
	
	output			BMC_VR_EN,											
	output			RST_SRST_BMC_PFR_N,		
	output			cc_PWRGD_AUX_PWRGD_CPU0,
	output			cc_PWRGD_AUX_PWRGD_CPU1,
	
	//SCM MAIN POWER RAIL
	input 			PWRGD_P5V_MAIN_SCM,
	output			oP5V_MAIN_PWR_FAULT,
	output         oFM_P5V_MAIN_SCM_EN,
	
	//PLT LOGIC
	input 			RST_SRST_BMC_SCM_FPGA_N,
	input 			RST_RTCRST_TTK3_N,
	input 			BMC_CMOS_CLEAR_N,
	input 			PARTITION_DEBUG_SEL,
	input 			FM_DUAL_PARTITION_R_N,
	input 			FM_PARTITION_SEL_R,
	input          iRST_BMC_SRST_DIO_N,
	
	output         PARTITION_DEBUG_SEL_OUT,
	output         FM_VOLTAGE_TRANSLATOR_EN,
	output         PWRGD_AUX_PWRGD_BMC_CPU0,
	
	//DC-SCM
	input 			HPM_STBY_RDY,
	
	//PFR related
	input 			RST_PLTRST_CPU0_PFR_LVC3_N,			//PLTRST back from PFR		
	input 			RST_PLTRST_CPU1_PFR_LVC3_N,
	input 			PWRGD_AUX_PWRGD_CPU0,					//AUX_PWRGD back from PFR
	input 			PWRGD_AUX_PWRGD_CPU1,
	input 			RST_BMC_RSTBTN_OUT_N,					//BMC SRST from PFR
	input 			RST_PFR_RTCRST_CPU0_N,					//RTC RST from PFR
	input 			RST_PFR_RTCRST_CPU1_N,
	
	//Signals from CPU FPGA thru LVDS
	input          iPWRGD_PS_PWROK_CPU_PLD_R,
	
	//Signals directly pass thru LVDS to CPU FPGA
	input 			RST_BMC_PCIE_MUX_N,
	input 			RST_BMC_HSBP_MUX_N,
	input 			FM_BMC_ONCTL_N,
	input 			FP_BMC_PWR_BTN_OUT_N,
	input 			FM_BMC_BMCINIT,
	input 			FP_ID_LED_N,
	input 			FP_LED_STATUS_AMBER_N,
	input 			FP_LED_STATUS_GREEN_N,
	input 			SPEAKER_BMC,
	input 			FM_SKT0_FAULT_LED,
	input 			FM_SKT1_FAULT_LED,
	input 			FM_CPU_FBRK_DEBUG_N,
	input 			FM_SPD_SWITCH_CTRL_N,
	input 			FM_TPM_EN_PULSE,
	input 			FM_LED_BMC_CPU_RSTIND,
	input 			A_P3V_BAT_SCALED_EN,
	input          FM_CK440_REMOTESSC_GPIO0,
	input          FM_CK440_REMOTESSC_GPIO1,
	input          FM_BMC_TRUST_N,
	
	output 			oRST_BMC_PCIE_MUX_N,
	output 			oRST_BMC_HSBP_MUX_N,
	output 			oFM_BMC_ONCTL_N,
	output 			oFP_BMC_PWR_BTN_OUT_N,
	output 			oFM_BMC_BMCINIT,
	output 			oFP_ID_LED_N,
	output 			oFP_LED_STATUS_AMBER_N,
	output 			oFP_LED_STATUS_GREEN_N,
	output 			oSPEAKER_BMC,
	output 			oFM_SKT0_FAULT_LED,
	output 			oFM_SKT1_FAULT_LED,
	output 			oFM_CPU_FBRK_DEBUG_N,
	output 			oFM_SPD_SWITCH_CTRL_N,
	output 			oFM_TPM_EN_PULSE,
	output 			oFM_LED_BMC_CPU_RSTIND,
	output 			oA_P3V_BAT_SCALED_EN,
	output         oRST_BMC_RSTBTN_OUT_N,
	output         oFM_CK440_REMOTESSC_GPIO0,
	output         oFM_CK440_REMOTESSC_GPIO1,
	output         oFM_BMC_TRUST_N,
	
	
	//Signals be used  both inside dcscm_main.v module and pss thru to LVDS 
	output			oRST_RTC_RST_CPU0,					   //Internal logic generate, tunnel to LVDS
	output			oRST_RTC_RST_CPU1,					   //Internal logic generate, tunnel to LVDS
	output			oSCM_BMC_AUX_PWR_OK,						//Internal logic generate, tunnel to LVDS
	output			oSCM_BMC_AUX_PWR_FAULT,					//Internal logic generate, tunnel to LVDS
	output			oSCM_PWR_FAULT,							//Internal logic generate, tunnel to LVDS
	output			oBMC_PWR_FAULT,							//Internal logic generate, tunnel to LVDS
	output			oRST_PLTRST_CPU0_PFR_LVC3_N,			//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
	output			oRST_PLTRST_CPU1_PFR_LVC3_N,			//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
	output			oPWRGD_AUX_PWRGD_CPU0,					//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
	output			oPWRGD_AUX_PWRGD_CPU1,					//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
	output			oFM_DUAL_PARTITION_R_N,					//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
	output			oFM_PARTITION_SEL_R,						//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
	output		[7:0]   oSCMFPGAREV,
	output		[7:0]   oSCMFPGATEST

);

//////////////////////////////////////////////////////////////////
//Internal signals
//////////////////////////////////////////////////////////////////

//SCM_AUX
	wire				wSCM_BMC_AUX_PWR_OK;		//to CPU PLD thru LVDS
	wire				wSCM_BMC_AUX_PWR_FAULT;	//to CPU PLD thru LVDS
	wire				wSCM_PWR_FAULT;			//to CPU PLD thru LVDS
	wire				wBMC_PWR_FAULT;			//to CPU PLD thru LVDS

//Internal inputs, GlitchFilter'ed
	//SM AUX
	wire 				PWRGD_P1V05_SCM_AUX_FF;
	wire 				PWRGD_P1V0_BMC_AUX_FF;
	wire 				RST_DEDI_BUSY_CPU0_N_FF;
	wire 				RST_DEDI_BUSY_CPU1_N_FF;
	
	//SCM MAIN POWER RAIL
	wire 				PWRGD_P5V_MAIN_SCM_FF;
	
	//PLT LOGIC
	wire 				RST_SRST_BMC_SCM_FPGA_N_FF;
	wire 				RST_RTCRST_TTK3_N_FF;
	wire 				BMC_CMOS_CLEAR_N_FF;
	wire 				PARTITION_DEBUG_SEL_FF;
	wire 				FM_DUAL_PARTITION_R_N_FF;
	wire 				FM_PARTITION_SEL_R_FF;
	
	//DC-SCM SPEC
	wire 				HPM_STBY_RDY_FF;
	
	//PFR related
	wire 				RST_PLTRST_CPU0_PFR_LVC3_N_FF;			//PLTRST back from PFR		
	wire 				RST_PLTRST_CPU1_PFR_LVC3_N_FF;
	wire 				PWRGD_AUX_PWRGD_CPU0_FF;					//AUX_PWRGD back from PFR
	wire 				PWRGD_AUX_PWRGD_CPU1_FF;
	wire 				RST_BMC_RSTBTN_OUT_N_FF;					//BMC SRST from PFR
	wire 				RST_PFR_RTCRST_CPU0_N_FF;					//RTC RST from PFR
	wire 				RST_PFR_RTCRST_CPU1_N_FF;
	
	//TXS_OE pin related
	wire        wDoneTimer1msOE;
	reg         rFM_VOLTAGE_TRANSLATOR_EN;
	
	parameter   T_1mS_OE_2M     =   12'd2000;

//////////////////////////////////////////////////////////////////
//Instance
//////////////////////////////////////////////////////////////////

//Input signals used in internal module
	GlitchFilter # 
   (
	.NUMBER_OF_SIGNALS(20), .RST_VALUE(20'b0001_1001_1010_0000_0011)
	)synch_scm_input_internal                     //for inputs signals internal 
   (
      .iClk(iClk_2M),                     		//input clock
      .iARst_n(iRST_N),                   		//asynch reset signal active low
      .iEna(1'b1),                        		//enable signal to capture into the FFs (active high)
      .iSRst_n(1'b1),  									//sync rst, when is low, output is reset
      .iSignal({
                                iCPU1_AUX_PWR_OK,
								PWRGD_P1V05_SCM_AUX,
								PWRGD_P1V0_BMC_AUX,
								RST_DEDI_BUSY_CPU0_N,//0001
								
								RST_DEDI_BUSY_CPU1_N,
								PWRGD_P5V_MAIN_SCM,
								RST_SRST_BMC_SCM_FPGA_N,
								RST_RTCRST_TTK3_N,//1001
								
								BMC_CMOS_CLEAR_N,
								PARTITION_DEBUG_SEL,
								FM_DUAL_PARTITION_R_N,
								FM_PARTITION_SEL_R,//1010
								
								HPM_STBY_RDY,
								RST_PLTRST_CPU0_PFR_LVC3_N,
								RST_PLTRST_CPU1_PFR_LVC3_N,
								PWRGD_AUX_PWRGD_CPU0,//0000
								
								PWRGD_AUX_PWRGD_CPU1,
								RST_BMC_RSTBTN_OUT_N,
								RST_PFR_RTCRST_CPU0_N,
								RST_PFR_RTCRST_CPU1_N//0011
								 }),
      
      .oFilteredSignals({
                                iCPU1_AUX_PWR_OK_FF,
								PWRGD_P1V05_SCM_AUX_FF,
								PWRGD_P1V0_BMC_AUX_FF,
								RST_DEDI_BUSY_CPU0_N_FF,
								RST_DEDI_BUSY_CPU1_N_FF,
								PWRGD_P5V_MAIN_SCM_FF,
								RST_SRST_BMC_SCM_FPGA_N_FF,
								RST_RTCRST_TTK3_N_FF,
								BMC_CMOS_CLEAR_N_FF,
								PARTITION_DEBUG_SEL_FF,
								FM_DUAL_PARTITION_R_N_FF,
								FM_PARTITION_SEL_R_FF,
								HPM_STBY_RDY_FF,
								RST_PLTRST_CPU0_PFR_LVC3_N_FF,
								RST_PLTRST_CPU1_PFR_LVC3_N_FF,
								PWRGD_AUX_PWRGD_CPU0_FF,
								PWRGD_AUX_PWRGD_CPU1_FF,
								RST_BMC_RSTBTN_OUT_N_FF,
								RST_PFR_RTCRST_CPU0_N_FF,
								RST_PFR_RTCRST_CPU1_N_FF
								 })                         
      );	

//Input signals directly tunnel to LVDS after GlitchFilter'ed
	GlitchFilter # 
   (
	.NUMBER_OF_SIGNALS(22), .RST_VALUE(22'b00_0001_1001_1010_0000_0011)
	)synch_scm_input_lvds                     //for inputs signals internal 
   (
      .iClk(iClk_2M),                     		//input clock
      .iARst_n(iRST_N),                   		//asynch reset signal active low
      .iEna(1'b1),                        		//enable signal to capture into the FFs (active high)
      .iSRst_n(1'b1),  									//sync rst, when is low, output is reset
      .iSignal({
								FM_BMC_TRUST_N,
								FM_CK440_REMOTESSC_GPIO0,
								FM_CK440_REMOTESSC_GPIO1,
								RST_BMC_PCIE_MUX_N,
								RST_BMC_HSBP_MUX_N,
								FM_BMC_ONCTL_N,
								FP_BMC_PWR_BTN_OUT_N,
								FM_BMC_BMCINIT,
								FP_ID_LED_N,
								FP_LED_STATUS_AMBER_N,
								FP_LED_STATUS_GREEN_N,
								SPEAKER_BMC,
								FM_SKT0_FAULT_LED,
								FM_SKT1_FAULT_LED,
								FM_CPU_FBRK_DEBUG_N,
								FM_SPD_SWITCH_CTRL_N,
								FM_TPM_EN_PULSE,
								FM_LED_BMC_CPU_RSTIND,
								A_P3V_BAT_SCALED_EN
								 }),
      
      .oFilteredSignals({
		                  oFM_BMC_TRUST_N,
								oFM_CK440_REMOTESSC_GPIO0,
								oFM_CK440_REMOTESSC_GPIO1,
								oRST_BMC_PCIE_MUX_N,
								oRST_BMC_HSBP_MUX_N,
								oFM_BMC_ONCTL_N,
								oFP_BMC_PWR_BTN_OUT_N,
								oFM_BMC_BMCINIT,
								oFP_ID_LED_N,
								oFP_LED_STATUS_AMBER_N,
								oFP_LED_STATUS_GREEN_N,
								oSPEAKER_BMC,
								oFM_SKT0_FAULT_LED,
								oFM_SKT1_FAULT_LED,
								oFM_CPU_FBRK_DEBUG_N,
								oFM_SPD_SWITCH_CTRL_N,
								oFM_TPM_EN_PULSE,
								oFM_LED_BMC_CPU_RSTIND,
								oA_P3V_BAT_SCALED_EN
								 })                         
      );	
		

//SCM_AUX
    scm_aux scm_aux_inst(
        .iClk                   ( iClk_2M                   ),
        .iRst_n                 ( iRST_N                    ),
        .iAUX_SEQ_EN            ( iSCM_BMC_EN               ),
        .iPWRGD_P1V05_SCM_AUX   ( PWRGD_P1V05_SCM_AUX_FF    ),      // From P1V05 SCM AUX VR, since this is the last stage SCM card VR, so can indicate all SCM card VRs are fully on
        .iPWRGD_P1V0_BMC_AUX    ( PWRGD_P1V0_BMC_AUX_FF     ),      // From P1V0 BMC AUX VR, since this is the last stage runBMC card VR, so can indicate all runBMC card VRs are fully on
        .iRST_DEDI_BUSY_CPU0_N  ( RST_DEDI_BUSY_CPU0_N_FF   ),
        .iRST_DEDI_BUSY_CPU1_N  ( RST_DEDI_BUSY_CPU1_N_FF   ),
        .iRST_BMC_SRST_DIO_N    ( iRST_BMC_SRST_DIO_N       ),
        .iFM_HPM_STBY_RDY       ( HPM_STBY_RDY_FF           ),      // From main FPGA logic, indicate legacy processor VCCFA_EHV and VNN power rails are fully on
        .iCPU1_AUX_PWR_OK       ( iCPU1_AUX_PWR_OK_FF       ),      // From main FPGA through LTPI, indicate CPU1 AUX power rails are fully on
        
        .oBMC_VR_EN             ( BMC_VR_EN                 ),      // To runBMC card first stage VR, enable all runBMC card VRs stage by stage
        .oSCM_BMC_AUX_PWR_OK    ( wSCM_BMC_AUX_PWR_OK       ),      // To main FPGA through LTPI, indicate all VRs on SCM card and runBMC card are fully on
        .oSCM_BMC_AUX_PWR_FAULT ( wSCM_BMC_AUX_PWR_FAULT    ),      // To main FPGA logic through LTPI, indicate SCM card or runBMC card VR failure
        .oSCM_PWR_FAULT         ( wSCM_PWR_FAULT            ),      // To debug FPGA through LTPI and sGPIO, indicate SCM card VR failure for postcode display
        .oBMC_PWR_FAULT         ( wBMC_PWR_FAULT            ),      // To debug FPGA through LTPI and sGPIO, indicate runBMC card VR failure for postcode display
        .oRST_SRST_BMC_N        ( RST_SRST_BMC_PFR_N        ),      // To PFR, indicate all VRs on SCM card and runBMC card are fully on, can release BMC SRST#
        .oPWRGD_AUX_PWRGD_CPU0  ( cc_PWRGD_AUX_PWRGD_CPU0   ),      // To PFR, indicate legacy processor VCCFA_EHV and VNN power rails are fully on, can release CPU_AUX_PWRGD
        .oPWRGD_AUX_PWRGD_CPU1  ( cc_PWRGD_AUX_PWRGD_CPU1   )       // To PFR, indicate CPU1 VCCFA_EHV and VNN power rails are fully on, can release CPU1 AUX_PWRGD
        
    );

//P5V MAIN PWR
p5v_main_pwr p5v_main_pwr_inst(
   .iClk                          (iClk_2M), //clock for sequential logic 
	.iRst_n                        (iRST_N), //reset signal from PLL Lock, resets state machine to initial state

	.iPWRGD_PS_PWROK_CPU_PLD_R     (iPWRGD_PS_PWROK_CPU_PLD_R),		//PS_PWROK from MB to indicate P12V_MAIN is ready
	.iPWRGD_P5V_MAIN_SCM           (PWRGD_P5V_MAIN_SCM_FF),			   //PWRGD from P5 MAIN VR
	
	.oFM_P5V_MAIN_SCM_EN           (oFM_P5V_MAIN_SCM_EN),				//To enable P5V MAIN VR
	.oP5V_MAIN_PWR_FAULT           (oP5V_MAIN_PWR_FAULT)			   //indicate SCM P5V MAIN VR fault, need to tunnel to CPU FPGA thru LVDS
);	

//////////////////////////////////////////////////////////////////
//Combinational logic
//////////////////////////////////////////////////////////////////
	
	assign oSCM_BMC_AUX_PWR_OK 				=	wSCM_BMC_AUX_PWR_OK;							//Internal logic generate, tunnel to LVDS
	assign oSCM_BMC_AUX_PWR_FAULT 			=	wSCM_BMC_AUX_PWR_FAULT;						//Internal logic generate, tunnel to LVDS
	assign oSCM_PWR_FAULT 						=	wSCM_PWR_FAULT;								//Internal logic generate, tunnel to LVDS
	assign oBMC_PWR_FAULT 						=	wBMC_PWR_FAULT;								//Internal logic generate, tunnel to LVDS
	assign oRST_PLTRST_CPU0_PFR_LVC3_N 		=	RST_PLTRST_CPU0_PFR_LVC3_N_FF;			//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
	assign oRST_PLTRST_CPU1_PFR_LVC3_N 		=	RST_PLTRST_CPU1_PFR_LVC3_N_FF;			//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
	assign oPWRGD_AUX_PWRGD_CPU0 				=	PWRGD_AUX_PWRGD_CPU0_FF;					//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
	assign oPWRGD_AUX_PWRGD_CPU1 				=	PWRGD_AUX_PWRGD_CPU1_FF;					//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
	assign oFM_DUAL_PARTITION_R_N 			=	FM_DUAL_PARTITION_R_N_FF;					//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
	assign oFM_PARTITION_SEL_R 				=	FM_PARTITION_SEL_R_FF;						//GlitchFilter'ed, signal used both by internal module and tunnel to LVDS
	assign oRST_BMC_RSTBTN_OUT_N           =  RST_BMC_RSTBTN_OUT_N_FF;               //GlitchFilter'ed, signal used both by internal module and tunnel to LVDS    
	
	assign PARTITION_DEBUG_SEL_OUT         =  PARTITION_DEBUG_SEL_FF;
	
	assign PWRGD_AUX_PWRGD_BMC_CPU0        =  PWRGD_AUX_PWRGD_CPU0_FF;
	//RTC logic to MB (active high on MB)
	
	assign oRST_RTC_RST_CPU0               =  ~(RST_PFR_RTCRST_CPU0_N_FF && RST_RTCRST_TTK3_N_FF);
	assign oRST_RTC_RST_CPU1               =  ~RST_PFR_RTCRST_CPU1_N_FF;
	
	assign oSCMFPGAREV                     =  SCM_FPGA_REV;
	assign oSCMFPGATEST                    =  SCM_FPGA_REV_TEST;

//TXS OE pin logic
	
	always @(posedge iClk_2M or negedge iRST_N) begin
	   if(!iRST_N) begin
		   rFM_VOLTAGE_TRANSLATOR_EN          <=   1'b1;
		end
		else begin
		   if(wDoneTimer1msOE) begin
			   rFM_VOLTAGE_TRANSLATOR_EN       <=   1'b0;
			end
		end
	end

   assign      FM_VOLTAGE_TRANSLATOR_EN       =   rFM_VOLTAGE_TRANSLATOR_EN;
	
	// Delay for TXS OE pin

   delay #(.COUNT(T_1mS_OE_2M)) 
     OE_1mS_DLY(
               .iClk(iClk_2M),
               .iRst(iRST_N),
               .iStart(RST_SRST_BMC_SCM_FPGA_N_FF),
               .iClrCnt(1'b0),
               .oDone(wDoneTimer1msOE)
               );	

endmodule

